Senior Digital Design Engineer

Description:

Seeking a highly motivated and innovative experienced Digital Design Engineer with knowledge of ASIC development flow. The candidate will be working as part of a highly experienced mixed-signal design and verification team, targeting next generation of our flagship PCIe and Ethernet PAM4 and NRZ PHY products.

PHY design development is very dynamic and provides an endless list of challenges. The candidate would undergo initial training by top experts in the field followed by continuous on the job training and assignments. The work is very challenging, with new and interesting mixed signal design aspects to address frequently. These technological challenges will continue to bring on additional responsibilities and task ownership.

Key Qualifications
 

• Master plus 5+ years of relevant digital design experience in the industry
• Scripting experience in Shell, Perl, Python or TCL is a plus.
• Good theoretical and practical understanding of digital signal processing and data recovery circuits.
• Excellent analytical skills to resolve challenges in creative ways and exercise unaided judgment in selecting methods and techniques to obtain solutions.
• Good communication skills for interacting with different design groups (example analog, P&R…) and customers.
• Must be self-motivated, proactive, and able to balance good design quality while meeting tight deadlines.
• Must exhibit ability to produce good results as an individual and team contributor.
   

Required Experience
 

• RTL coding, modeling of analog blocks, and/or writing complex system-level tests in Verilog or System Verilog
• Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools.
• Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures.
• Enhancing and maintaining existing SERDES PHY IPs supporting many protocols.
• Interacting with Application Engineers and/or customers to resolve complex technical issues