Senior Asic Verification Engineer

Description:

Headquartered in Ottawa, our client serves the electronic design community from Canada, specializing in ASIC and FPGA design and verification, and embedded software development services. We augment and enhance our clients’ teams and accelerate the development of complete designs.They are adaptable and efficient, with a brilliant staff at our core. They aim to be the best at what we do.

Our success continues to fuel growth. We are currently searching globally for a number of key technical resources, including a Senior ASIC Verification Engineer with deep expertise in UVM and SystemVerilog.

If you want to have an #adventure in #Canada, this might be the right role for you- Europeans, Israelis and some other nationalities does not need a long visa process! These candidates are highly welcomed.

Responsibilities:

• Prime the verification activities for a block or an entire chip.
• Develop verification environment architecture using UVM.
• Document test environment associations and write test cases.
• Employ constrained random verification approaches when possible.
• Support lab bring-up with direct test cases.
• Perform code and functional coverage.

Required Skills and Experience:

• 8+ years of experience in ASIC verification.
• Highly skilled in Verilog, SystemVerilog, other hardware description languages, and scripting languages.
• Significant experience with OVM/UVM methodologies.
• Familiarity with constrained random verification techniques, assertions and functional coverage.
• Experience with SONET, OTN, Ethernet, PCIe is a significant asset.
• Team player – excellent interpersonal and communication skills.