Interpret high-level requirements and transform them into meticulous specifications.
Design and execute RTL logic (predominantly Verilog or System Verilog), conduct block-level simulation, ASIC synthesis, DFT insertion, and ensure timing closure.
Over 8 years of relevant experience in progressively senior roles.
Proficiency in modern ASIC development, encompassing RTL logic design, synthesis, STA, lint, LEC, and proficiency in PnR.
Expertise in handling complex asynchronous clock boundaries and high-speed serial interfaces.
Familiarity with lab environments, adept at troubleshooting issues up to the system level.
Experience or familiarity with some of the following: Processor sub-systems (ARM, RISC-V), NOCs, GPUs, Display Interfaces, 10/25/40/100GbE, PCIe, AI Cores, Packet Processing, Routers/Switches.
Proficiency with industry-standard interfaces such as AHB, AXI, APB, AMBA, HDMI, DisplayPort, USB, Ethernet, PCIe, SPI, I2C, USB, GPIO, SRIO, DDR/SDRAM/DMA.